1. Field of the Invention
The present invention relates to a circuit for generating a sampling clock to stably sample a video signal and a display apparatus having the; circuit and in particular, to a circuit for generating a sampling clock to sample a video signal at the optimum timing to avoid edge business or jerkiness of a picture and a liquid crystal display apparatus.
2. Description of the Prior Art
Heretofore, a circuit for generating a sample clock used in a liquid crystal display apparatus which inputs a video signal from a personal computer adjusts a phase of the sampling clock in accordance with a switch operation by a user who intends to optimize the phase while watching the picture on the display panel. Such an adjustment is troublesome for the user. Therefore, automating the adjustment of a sample clock is required.
For example, JPA 10-161598 discloses a pixel synchronization apparatus in which a video signal is sampled with a sampling clock having a frequency multiple times as high as a reference clock, wherein a stable voltage period of the video signal is observed from the sampled video signal, and a phase of the sampling clock is adjusted.
FIG. 4 shows the structure of a liquid crystal display apparatus comprising the pixel synchronization apparatus disclosed in JPA 10-161598. Referring to FIG. 4, PLL (Phase-Locked Loop) circuit 1 outputs a reference clock which is synchronized with an input horizontal synchronization signal and is N times as high as a dot clock. Sampling circuit for detection 13 samples an analog video signal with the reference clock to output sampled data as DATA to stable-period-detecting circuit 14.
Stable-period-detecting circuit 14 detects whether a voltage of the sampled video signal varies and if the voltage does not vary, outputs a CS signal indicating a stable voltage period to controller 15. Controller 15 analyzes the CS signal and outputs a phase control signal for ensuring a setup time and a hold time in pixel data sampling circuit 3 to delay circuit 12. On the other hand, frequency divider 11 generates a first sampling clock having a frequency 1/N times as high as the reference clock to output the first sampling clock to delay circuit 12. Delay circuit 12 delays the first sampling clock by a delay time controlled by the phase control signal to output a second sampling clock SCLK to pixel-data-sampling circuit 3.
In the pixel synchronization apparatus disclosed in JPA 10-161598, although a quick adjustment to cope with a moving picture is realized, a disadvantage arises that an expensive PLL circuit and an expensive A/D converter, each of which operates at a frequency N times as high as a dot clock, are required. Moreover, because an internal operation frequency becomes high, another disadvantage arises that radiation of EMI noise increases.
In order to overcome the aforementioned disadvantages, the present invention has been made and accordingly, has an object to provide an inexpensive circuit for generating a sampling clock to stably sample a video signal which can automatically adjust a phase of the sampling clock without increasing the operation frequency thereof.
According to a first aspect of the present invention, there is provided a circuit for generating a sampling clock to stably sample a video signal in a pixel-data-sampling circuit, comprising: a sampling clock generator for generating a sampling clock which has the same frequency as a sampling frequency of the pixel-data-sampling circuit and is synchronized with a horizontal synchronization signal except for being delayed by a delay time designated by a control signal; a detector for detecting the worst sampling clock whose sampling edge coincides with a transition edge of the video signal; and means for generating the control signal to have the sampling clock generator generate the best sampling clock whose phase is at a straight angle to the phase of the worst sampling clock.
The sampling clock generator may comprise: a phase-locked loop for generating a dot clock which has the same frequency as the sampling frequency of the pixel-data-sampling circuit and is synchronized with the horizontal synchronization signal; and a delay circuit for delaying the dot clock by a delay time designated by the control signal to output a sampling clock which is delayed from the dot clock by the delay time.
The detector may comprise: a comparator for comparing a voltage of the video signal with a threshold voltage to output a binarized video signal; a counter for counting the number of sampling edges of the sampling clock from a positive edge of the horizontal synchronization signal to a positive edge of the binarized video signal; and a determiner for determining the worst sampling clock by examining the number of sample edges counted by the counter.
The detector may comprise: a comparator for comparing a voltage of the video signal with a threshold voltage to output a binarized video signal; a counter for counting the number of sampling edges of the sampling clock from a positive edge of the horizontal synchronization signal to a negative edge of the binarized video signal; and a determiner for determining the worst sampling clock by examining the number of sample edges counted by the counter.
The detector may comprise: a comparator for comparing a voltage of the video signal with a threshold voltage to output a binarized video signal; a counter for counting the number of sampling edges of the sampling clock from a negative edge of the horizontal synchronization signal to a positive edge of the binarized video signal; and a determiner for determining the worst sampling clock by examining the number of sample edges counted by the counter.
The detector may comprise: a comparator for comparing a voltage of the video signal with a threshold voltage to output a binarized video signal; a counter for counting the number of sampling edges of the sampling clock from a negative edge of the horizontal synchronization signal to a negative edge of the binarized video signal; and a determiner for determining the worst sampling clock by examining the number of sample edges counted by the counter.
The determiner may determine the worst sampling clock by detecting a delay of a sampling clock when the number of sampling edges is decremented by one while increasing the delay.
The determiner may determine the worst sampling clock by detecting a delay of a sampling clock when the number of sampling edges is incremented by one while decreasing the delay.
According to a second aspect of the present invention, there is provided a circuit for generating a sampling clock to stably sample a video signal in a pixel-data-sampling circuit, comprising: a sampling clock generator for generating a plurality of sampling clocks, each of which has the same frequency as a sampling frequency of the pixel-data-sampling circuit and is synchronized with a horizontal synchronization signal except for being delayed by a delay time, the delay times for a plurality of sampling clocks being shifted one another; a detector for detecting the worst sampling clock whose sampling edge coincides with a transition edge of the video signal among a plurality of sampling clocks; and means for selecting the best sampling clock whose phase is at a straight angle to the phase of the worst sampling clock among a plurality of sampling clocks.
The sampling clock generator may comprise: a phase-locked loop for generating a dot clock which has the same frequency as the sampling frequency of the pixel-data-sampling circuit and is synchronized with the horizontal synchronization signal; and a delay circuit for delaying the dot clock to output a plurality of sampling clocks which are delayed from the dot clock by delay times different from each other.
The detector may comprise: a comparator for comparing a voltage of the video signal with a threshold voltage to output a binarized video signal; a plurality of counters, each for counting the number of sampling edges of the corresponding sampling clock from a positive edge of the horizontal synchronization signal to a positive edge of the binarized video signal; and a determiner for determining the worst sampling clock by examining the number of sample edges counted by each counter.
The detector may comprise: a comparator for comparing a voltage of the video signal with a threshold voltage to output a binarized video signal; a plurality of counters, each for counting the number of sampling edges of the corresponding sampling clock from a positive edge of the horizontal synchronization signal to a negative edge of the binarized video signal; and a determiner for determining the worst sampling clock by examining the number of sample edges counted by each counter.
The detector may comprise: a comparator for comparing a voltage of the video signal with a threshold voltage to output a binarized video signal; a plurality of counters, each for counting the number of sampling edges of the corresponding sampling clock from a negative edge of the horizontal synchronization signal to a positive edge of the binarized video signal; and a determiner for determining the worst sampling clock by examining the number of sample edges counted by each counter.
The detector may comprise: a comparator for comparing a voltage of the video signal with a threshold voltage to output a binarized video signal; a plurality of counters, each for counting the number of sampling edges of the corresponding sampling clock from a negative edge of the horizontal synchronization signal to a negative edge of the binarized video signal; and a determiner for determining the worst sampling clock by examining the number of sample edges counted by each counter.
The determiner may determine the worst sampling clock by detecting a delay of a sampling clock when the number of sampling edges is decremented by one while the examined counter is shifted from the counter of a shorter delay time to the counter of a longer delay time.
The determiner may determine the worst sampling clock by detecting a delay of a sampling clock when the number of sampling edges is decremented by one while the examined counter is shifted from the counter of a longer delay time to the counter of a shorter delay time.
According to a third aspect of the present invention, there is provided a display apparatus, comprising: the above circuit for generating a sampling clock; a picture-data-sampling circuit for sampling a video signal with the sampling clock generated by the circuit for generating a sampling clock; a video signal processor for processing a sampled video signal; a driver for generating a drive signal on the basis of a vertical synchronization signal and a horizontal synchronization signal; and a display for displaying a picture on the basis of said sampled video signal by using said drive signal.
The display may be a liquid crystal display panel.